In a memory device, such as a dynamic random access memory (DRAM), information is stored in capacitors accessed via a transistor (i.e. transfer gate). The two different states this capacitor (i.e. charged or discharged) can be set to corresponding to the two different pieces of information needed in digital algebra, “true” and “false”. A variety of leakage currents may lead to a loss of information by discharging this capacitor without access being controlled. In order to take the proper corrective steps to improve the manufacturing process of the device, it may be beneficial to identify the primary causes of the leakage. It may be beneficial to distinguish between leakage related to failing cells (i.e. “soft fails”) from other failing cells (i.e. “hard fails”) in order to determine the appropriate corrective actions.
A standard DRAM design uses a wordline (WL)/bitline (BL) architecture, where a DRAM storage cell is addressed by a specific WL and a BL address. Process faults lead to failures in wordlines and/or bitlines, causing complete and/or partial WL and/or BL fails and/or other fail patterns like single cells, paired cells, etc. Fails in a very early state of WL/BL address decoding hierarchy of course lead to multiple WL or BL failures or even to failures of large memory cell blocks. Due to redundancy limitations, block fails may not be repairable, although sparse fails (WL, BL and single cell fails) can be repaired if not too densely packed.
Because of the reverse biased junction between a capacitor and p-well of the transfer device, a reverse current or junction leakage will decrease the amount of charge stored in the capacitor over time. In order to get correct results of a READ operation, the information stored in the capacitor cell has to be refreshed periodically. Leakage current and refresh intervals are synchronized so that the information stored will not dissipate, unless additional leakage will disturb this synchronization leading to soft fails. Typically, partial WL or BL fails turn into full WL or BL fails over time. In addition to the filled up WL and BL fails, some weak single cells (SC) and paired cells (PC) will start to fail with a longer time between the refresh cycles.
Because partial WL fails need to be repaired with a redundant WL element, the repair of the entire WL comes at no additional costs of redundant cells. However, unlike those fails of a partial WL or BL or a full WL or BL, single cell or paired cell fails are randomly distributed across the memory cell array and require one redundancy array (RA) element for each fail. Such single cell or paired cell fails can make it difficult to repair a cell, and therefore such information can be critical in determining whether a cell can be repaired.
Accordingly, there is a need for an improved system and method of analyzing cells of a memory device.